1. Field of the Invention
The present invention relates to a variable delay circuit which controls a delay circuit provided on a transfer path to vary the delay time of the delay circuit and to a semiconductor integrated circuit device having such a delay circuit.
The circuit design mainstream utilizes clock synchronization due to the recent progress towards increasing of the operation speed and the integration density. Hence, it becomes important to suitably supply a given circuit with a clock that is synchronized with an external clock signal. The latest art uses a DLL (Delay Locked Loop) circuit having the minimum delay time unit equal to approximately 200 ps in order to generate an internal clock which is synchronism with the external clock. As the frequency of the internal clock is increased, it is required that a variable delay circuit using the DLL circuit has a higher precision.
2. The Description of the Related Art
A description will now be given, with reference to FIG. 1, of a conventional variable delay circuit.
The circuit shown in FIG. 1 has a four-stage delay circuit consisting of first, second, third and fourth delay circuits 201, 202, 203 and 204, respectively.
The first delay circuit 201 includes gates G201 and G202, and the second delay circuit 202 includes gates G203, G204 and G205. The third delay circuit 203 includes gates G206, G207 and G208, and the fourth delay circuit 204 includes gates G209, G210 and G211. The first through fourth delay circuits 201 through 204 are supplied with switch input signals via switch terminals (SW) P203 through P206. One of the switch input signals is switched to a high level (H), an input clock signal applied to an input terminal P201 is delayed by a delay time based on which one of the switch input signals is switched to the high level. A resultant delayed clock signal is output via an output terminal P202. Each of the gates G201-G211 has a unit delay time 1td.
In the operation of the first delay circuit 201, the gate G201 is masked when the signal applied to the switch terminal P203 is at a low level (L). The output signal obtained at the output terminal 202 is always at the low level irrespective of whether the other input of the gate G201 is high or low. The gate 201 is released from the masked state when the signal applied to the switch terminal P203 is at the high level. If the potential of the other input of the gate G201 successively changes to the high level and the low level in this order, the output signal of the output terminal P202 is changed to the high level and the low level in this order. Hence, when the signal applied to the switch terminal P203 is at the high level, the delay time from the input terminal P201 to the output terminal P202 is equal to 2td because the input signal passes through the two stages of gates therebetween.
In the operation of the second delay circuit 202, the gate G203 is masked when the signal applied to the switch terminal P204 is at the low level. The output signal of the output terminal P202 is always at the low level irrespective of whether the other input of the gate G203 is high or low. The gate 203 is released from the masked state when the signal applied to the switch terminal P204 is at the high level. If the potential of the other input of the gate G203 successively changes to the high level and the low level in this order, the output signal of the output terminal P202 is changed to the high level and the low level in this order. Hence, when the signal applied to the switch terminal P204 is at the high level, the delay time from the input terminal P201 to the output terminal P202 is equal to 4td because the input signal passes through the four stages of gates therebetween.
Similarly, the output signal of the output terminal P202 obtained when the third delay circuit 203 or the fourth delay circuit 204 is activated by the switch signal applied to the switch terminal P205 or P206, respectively. If the switch signal applied to the switch terminal P205 is at the high level, the delay time provided from the input terminal P201 to the output terminal P202 is equal to 6td, which corresponds to 6 gates. When the switch signal applied to the switch terminal P206 is at the high level, the delay time from the input terminal P201 to the output terminal P202 is equal to 8td, which corresponds to 8 gates.
Hence, the conventional variable delay circuit having four stages of delay circuits is capable of providing the variable times equal to 2td to 8td.
A description will now be given, with reference to FIG. 2, of a conventional DLL circuit utilizing the above-mentioned conventional variable delay circuit.
Referring to FIG. 2, a conventional DLL circuit 210 includes a variable delay circuit 212, a phase comparator circuit 215, and a delay control circuit 216. The variable delay circuit 212 delays an external clock signal received by an input circuit 211 by a given delay time, and outputs the delayed external clock signal to an output circuit 213. The phase comparator circuit 215 compares the phase of a reference signal "ref" supplied from the input circuit 211 with the phase of a signal "in" output by a dummy circuit 214. The signal output by the dummy circuit 214 has a delay time equal to the sum of the delay times of the input circuit 211, the variable delay circuit 212 and the output circuit 213 and the delay times of wiring lines provided between the input circuit 211 and the output circuit 213. The conventional DLL circuit 210 thus configured functions to delay the clock signal from the input circuit 211 with a precision of approximately 200 ps so that the output clock signal having a predetermined phase relationship with the clock signal from the input circuit 211.
A description will now be given, with reference to FIG. 3, of a phase setting process of the DLL circuit 210. In FIG. 3, a symbol "ref" denotes the reference signal output by the input circuit 211, and a symbol "in" denotes the signal output by the dummy circuit 214. The DLL circuit 210 delays the external clock received via the input circuit 211 by a given delay time through the variable delay circuit 212. The output circuit 213 receives the delayed clock signal from the variable delay circuit 212 and supplies a circuit of the following stage with the clock signal which has been pulled in phase with the external clock signal.
The dummy circuit 214 supplies the phase comparator circuit 215 with the signal "in" having the same delay time as that equal to the sum of the delay times of the input circuit 211, the variable delay circuit 212 and the output circuit 213 and the delay times of the wiring lines provided therebetween (step S101). The input circuit 211 outputs, as the reference signal "ref", the external clock signal to the phase comparator circuit 215 (step S101). The phase comparator circuit 215 determines whether the signals "ref" and "in" are in phase (step S102). If the signals "ref" and "in" are out of phase, the relative phase relationship therebetween is determined (step S102).
If the signals "ref" and "in" are in phase ("just" at step S102), the delay control circuit 216 holds the current delay time of the variable delay circuit 212, and the phase comparator circuit 215 periodically performs the phase comparing operation.
If it is discerned, at step S102, that the signal "ref" from the input circuit 211 lags behind the signal "in" ("-1" at step S102), the phase comparator circuit 215 detects the phase difference therebetween. The delay control circuit 216 controls, based on the detected phase difference, the variable delay circuit 212 to reduce the delay time one stage by one stage (step S103). Then, the process returns to step S101 so that the steps S101 and S102 via step S103 are repeatedly carried out at predetermined intervals.
If it is discerned, at step S102, that the signal "in" from the dummy circuit 214 lags behind the signal "ref" ("+1" of step S102), the phase comparator circuit 215 detects the phase difference therebetween. The delay control circuit 216 controls, based on the detected phase difference, the variable delay circuit 212 to increase the delay time one stage by one stage (step S104). Then, the process returns to step S101 so that the steps S101 and S102 via step S104 are repeatedly carried out at predetermined intervals.
However, the conventional variable delay circuits as shown in FIG. 1 have a disadvantage in which a delay time shorter than the unit delay time 2td, for example, a delay time 1td cannot be obtained and the precision is restricted to 2td.